Fix other architectures compiling - haven't tried *running* anything..

6 files changed, 85 insertions, 74 deletions

diff --git a/lib/arm/dis-arm.inc.h b/lib/arm/dis-arm.inc.h
index 8f4d776..3ae0ab9 100644
--- a/lib/arm/dis-arm.inc.h
+++ b/lib/arm/dis-arm.inc.h
@@ -71,7 +71,7 @@ static INLINE void P(GPR_Rt_addr_offset_none_addr_postidx_imm8_offset_S_1_STRHTi
     data(r(addr), r(Rt));
 }
 static INLINE void P(GPR_Rt_addrmode3_addr_S_2_STRD)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
-    unsigned addr_val = bs_get(addr, ctx->op);
+    unsigned addr_val = bs_get(addr, ctx->base.op);
     if (addr_val & 1 << 13)
         data_flags(DFLAG_IS_LDRD_STRD, r(Rt), rs(addr, 9, 4));
     else
@@ -131,7 +131,7 @@ static INLINE void P(addr_offset_none_addr_unk_Rt_13_LDA)(tdis_ctx ctx, struct b
 }
 static INLINE void P(addrmode3_addr_unk_Rt_4_LDRD)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
     /* ignoring Rt2 = Rt + 1, but LDRD itself isn't supposed to load PC anyway */
-    unsigned addr_val = bs_get(addr, ctx->op);
+    unsigned addr_val = bs_get(addr, ctx->base.op);
     if (addr_val & 1 << 13)
         data_flags(DFLAG_IS_LDRD_STRD, rout(Rt), rs(addr, 9, 4));
     else
@@ -159,11 +159,12 @@ static INLINE void P(addrmode_imm12_pre_addr_unk_Rt_2_LDRB_PRE_IMM)(tdis_ctx ctx
     data(rout(Rt), rs(addr, 13, 4));
 }
 static INLINE void P(adrlabel_label_unk_Rd_1_ADR)(tdis_ctx ctx, struct bitslice label, struct bitslice Rd) {
-    return P(pcrel)(ctx, ctx->pc + 8 + bs_get(label, ctx->op), bs_get(Rd, ctx->op), PLM_ADR);
+    return P(pcrel)(ctx, ctx->base.pc + 8 + bs_get(label, ctx->base.op),
+                    (struct arch_pcrel_info) {bs_get(Rd, ctx->base.op), PLM_ADR});
 }
 static INLINE void P(br_target_target_pred_p_B_1_Bcc)(tdis_ctx ctx, struct bitslice target, struct bitslice p) {
-    unsigned p_val = bs_get(p, ctx->op);
-    return P(branch)(ctx, ctx->pc + 8 + sext(bs_get(target, ctx->op), 24),
+    unsigned p_val = bs_get(p, ctx->base.op);
+    return P(branch)(ctx, ctx->base.pc + 8 + sext(bs_get(target, ctx->base.op), 24),
                      p_val == 0xe ? 0 : (CC_ARMCC | p_val));
 }
 static INLINE void P(ldst_so_reg_addr_unk_Rt_2_LDRB_PRE_REG)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
@@ -182,13 +183,13 @@ static INLINE void P(unk_Rt_13_MRC)(tdis_ctx ctx, struct bitslice Rt) {
     data(rout(Rt));
 }
 static INLINE void P(GPR_Rn_reglist_regs_16_LDMDA)(tdis_ctx ctx, struct bitslice regs, UNUSED struct bitslice Rn) {
-    unsigned regs_val = bs_get(regs, ctx->op);
+    unsigned regs_val = bs_get(regs, ctx->base.op);
     if (regs_val & (1 << 15))
         return P(ret)(ctx);
     return P(unidentified)(ctx);
 }
 static INLINE void P(GPR_Rn_reglist_regs_S_16_STMDA)(tdis_ctx ctx, UNUSED struct bitslice regs, UNUSED struct bitslice Rn) {
-    unsigned regs_val = bs_get(regs, ctx->op);
+    unsigned regs_val = bs_get(regs, ctx->base.op);
     if (regs_val & (1 << 15))
         return P(bad)(ctx);
     return P(unidentified)(ctx);
@@ -207,8 +208,8 @@ static INLINE void P(GPR_dst_B_2_BX)(tdis_ctx ctx, UNUSED struct bitslice dst) {
 }
 
 static INLINE void P(dis_arm)(tdis_ctx ctx) {
-    uint32_t op = ctx->op = *(uint32_t *) ctx->ptr;
-    ctx->op_size = 4;
+    uint32_t op = ctx->base.op = *(uint32_t *) ctx->base.ptr;
+    ctx->base.op_size = ctx->base.newop_size = 4;
     #include "../generated/generic-dis-arm.inc.h"
     __builtin_abort();
 }
diff --git a/lib/arm/dis-main.inc.h b/lib/arm/dis-main.inc.h
index bf2767e..c9fe983 100644
--- a/lib/arm/dis-main.inc.h
+++ b/lib/arm/dis-main.inc.h
@@ -4,7 +4,7 @@
 
 static INLINE void P(dis)(tdis_ctx ctx) {
     if (ctx->arch.pc_low_bit) {
-        uint16_t op = *(uint16_t *) ctx->ptr;
+        uint16_t op = *(uint16_t *) ctx->base.ptr;
         bool is_32 = (op >> 13 & 7) == 7 && (op >> 11 & 3) != 0;
         if (is_32)
             return P(dis_thumb2)(ctx);
diff --git a/lib/arm/dis-thumb.inc.h b/lib/arm/dis-thumb.inc.h
index 72865cf..6b6e841 100644
--- a/lib/arm/dis-thumb.inc.h
+++ b/lib/arm/dis-thumb.inc.h
@@ -11,7 +11,7 @@ static INLINE void P(GPR_Rm_1_tADDspr)(tdis_ctx ctx, UNUSED struct bitslice Rm)
     return P(unidentified)(ctx);
 }
 static INLINE void P(GPR_Rm_B_1_tBX)(tdis_ctx ctx, struct bitslice Rm) {
-    unsigned val = bs_get(Rm, ctx->op);
+    unsigned val = bs_get(Rm, ctx->base.op);
     if (val == 15) /* bx pc */
         return P(bad)(ctx);
     else if (val == 14) /* bx lr */
@@ -19,13 +19,14 @@ static INLINE void P(GPR_Rm_B_1_tBX)(tdis_ctx ctx, struct bitslice Rm) {
     return P(unidentified)(ctx);
 }
 static INLINE void P(GPR_Rm_unk_Rd_1_tMOVr)(tdis_ctx ctx, struct bitslice Rd, struct bitslice Rm) {
-    unsigned Rd_val = bs_get(Rd, ctx->op);
-    unsigned Rm_val = bs_get(Rm, ctx->op);
+    unsigned Rd_val = bs_get(Rd, ctx->base.op);
+    unsigned Rm_val = bs_get(Rm, ctx->base.op);
     /* does anyone do this? */
     if (Rd_val == 15)
         return P(bad)(ctx);
     if (Rm_val == 15)
-        return P(pcrel)(ctx, ctx->pc + 4, Rd_val, PLM_ADR);
+        return P(pcrel)(ctx, ctx->base.pc + 4,
+                        (struct arch_pcrel_info) {Rd_val, PLM_ADR});
     return P(unidentified)(ctx);
 }
 static INLINE void P(tGPR_Rn_reglist_regs_1_tLDMIA)(tdis_ctx ctx, UNUSED struct bitslice regs, UNUSED struct bitslice Rn) {
@@ -35,7 +36,7 @@ static INLINE void P(tGPR_Rn_reglist_regs_S_1_tSTMIA_UPD)(tdis_ctx ctx, UNUSED s
     return P(unidentified)(ctx);
 }
 static INLINE void P(reglist_regs_1_tPOP)(tdis_ctx ctx, struct bitslice regs) {
-    unsigned regs_val = bs_get(regs, ctx->op);
+    unsigned regs_val = bs_get(regs, ctx->base.op);
     if(regs_val & (1 << 15))
         return P(ret)(ctx);
     return P(unidentified)(ctx);
@@ -44,34 +45,36 @@ static INLINE void P(reglist_regs_S_1_tPUSH)(tdis_ctx ctx, UNUSED struct bitslic
     return P(unidentified)(ctx);
 }
 static INLINE void P(t_addrmode_pc_addr_unk_Rt_1_tLDRpci)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
-    return P(pcrel)(ctx, ((ctx->pc + 4) & ~2) + bs_get(addr, ctx->op), bs_get(Rt, ctx->op), PLM_U32);
+    return P(pcrel)(ctx, ((ctx->base.pc + 4) & ~2) + bs_get(addr, ctx->base.op),
+                    (struct arch_pcrel_info) {bs_get(Rt, ctx->base.op), PLM_U32});
 }
 static INLINE void P(t_adrlabel_addr_unk_Rd_1_tADR)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rd) {
-    return P(pcrel)(ctx, ((ctx->pc + 4) & ~2) + bs_get(addr, ctx->op), bs_get(Rd, ctx->op), PLM_ADR);
+    return P(pcrel)(ctx, ((ctx->base.pc + 4) & ~2) + bs_get(addr, ctx->base.op),
+                    (struct arch_pcrel_info) {bs_get(Rd, ctx->base.op), PLM_ADR});
 }
 static INLINE void P(t_bcctarget_target_pred_p_B_1_tBcc)(tdis_ctx ctx, struct bitslice target, struct bitslice p) {
-    return P(branch)(ctx, ctx->pc + 4 + 2 * sext(bs_get(target, ctx->op), 8),
-                     CC_ARMCC | bs_get(p, ctx->op));
+    return P(branch)(ctx, ctx->base.pc + 4 + 2 * sext(bs_get(target, ctx->base.op), 8),
+                     CC_ARMCC | bs_get(p, ctx->base.op));
 }
 static INLINE void P(t_brtarget_target_B_1_tB)(tdis_ctx ctx, struct bitslice target) {
     int cc = ctx->arch.it_conds[0] != 0xe ? CC_ALREADY_IN_IT : 0;
-    return P(branch)(ctx, ctx->pc + 4 + 2 * sext(bs_get(target, ctx->op), 11), cc);
+    return P(branch)(ctx, ctx->base.pc + 4 + 2 * sext(bs_get(target, ctx->base.op), 11), cc);
 }
 static INLINE void P(t_cbtarget_target_B_2_tCBNZ)(tdis_ctx ctx, struct bitslice target) {
-    P(branch)(ctx, ctx->pc + 4 + 2 * bs_get(target, ctx->op), CC_CBXZ);
-    if (TDIS_CTX_MODIFY(ctx)) {
+    P(branch)(ctx, ctx->base.pc + 4 + 2 * bs_get(target, ctx->base.op), CC_CBXZ);
+    if (ctx->base.modify) {
         /* change target, and flip z/nz if necessary (i.e. always) */
-        int new_target = (TDIS_CTX_NEWVAL(ctx, 0) - (ctx->pc + 4)) / 2;
-        unsigned new = bs_set(target, new_target, ctx->op);
-        if (TDIS_CTX_NEWVAL(ctx, 1))
+        int new_target = (ctx->base.newop[0] - (ctx->base.pc + 4)) / 2;
+        unsigned new = bs_set(target, new_target, ctx->base.op);
+        if (ctx->base.newop[1])
             new ^= 1 << 11;
-        TDIS_CTX_SET_NEWOP(ctx, new);
+        *(uint32_t *) ctx->base.newop = new;
     }
 }
 static INLINE void P(it_pred_cc_it_mask_mask_1_t2IT)(tdis_ctx ctx, struct bitslice mask, struct bitslice cc) {
     /* why */
-    unsigned mask_val = bs_get(mask, ctx->op);
-    unsigned cc_val = bs_get(cc, ctx->op);
+    unsigned mask_val = bs_get(mask, ctx->base.op);
+    unsigned cc_val = bs_get(cc, ctx->base.op);
     if (mask_val == 0)
         return P(unidentified)(ctx); /* nop */
     int length = 4 - __builtin_ctz(mask_val);
@@ -82,13 +85,13 @@ static INLINE void P(it_pred_cc_it_mask_mask_1_t2IT)(tdis_ctx ctx, struct bitsli
 }
 
 static INLINE void P(thumb_do_it)(tdis_ctx ctx) {
-    uint16_t op = ctx->op = *(uint16_t *) ctx->ptr;
+    uint16_t op = ctx->base.op = *(uint16_t *) ctx->base.ptr;
     #include "../generated/generic-dis-thumb.inc.h"
     __builtin_abort();
 }
 
 static INLINE void P(dis_thumb)(tdis_ctx ctx) {
-    ctx->op_size = 2;
+    ctx->base.op_size = ctx->base.newop_size = 2;
     P(thumb_do_it)(ctx);
     advance_it_cond(&ctx->arch);
 }
diff --git a/lib/arm/dis-thumb2.inc.h b/lib/arm/dis-thumb2.inc.h
index 6f651c5..43ca4ab 100644
--- a/lib/arm/dis-thumb2.inc.h
+++ b/lib/arm/dis-thumb2.inc.h
@@ -19,7 +19,7 @@ static INLINE void P(GPR_Rm_unk_Rd_1_t2MOVr)(tdis_ctx ctx, struct bitslice Rm, s
     data(rout(Rd), r(Rm));
 }
 static INLINE void P(GPR_Rn_reglist_regs_4_t2LDMDB)(tdis_ctx ctx, struct bitslice regs, UNUSED struct bitslice Rn) {
-    unsigned regs_val = bs_get(regs, ctx->op);
+    unsigned regs_val = bs_get(regs, ctx->base.op);
     if(regs_val & (1 << 15))
         return P(ret)(ctx);
     return P(unidentified)(ctx);
@@ -88,8 +88,8 @@ static INLINE void P(addrmode5_pre_addr_S_4_t2STC2L_PRE)(tdis_ctx ctx, struct bi
     data(rs(addr, 9, 4));
 }
 static INLINE void P(brtarget_target_pred_p_B_1_t2Bcc)(tdis_ctx ctx, struct bitslice target, struct bitslice p) {
-    return P(branch)(ctx, ctx->pc + 4 + 2 * sext(bs_get(target, ctx->op), 20), 
-                     CC_ARMCC | bs_get(p, ctx->op));
+    return P(branch)(ctx, ctx->base.pc + 4 + 2 * sext(bs_get(target, ctx->base.op), 20), 
+                     CC_ARMCC | bs_get(p, ctx->base.op));
 }
 static INLINE void P(rGPR_Rt_t2addrmode_imm0_1020s4_addr_unk_Rd_S_1_t2STREX)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt, struct bitslice Rd) {
     data(rout(Rd), r(Rt), rs(addr, 8, 4));
@@ -146,14 +146,19 @@ static INLINE void P(t2addrmode_so_reg_addr_unk_Rt_5_t2LDRBs)(tdis_ctx ctx, stru
     data(rout(Rt), rs(addr, 6, 4), rs(addr, 2, 4));
 }
 static INLINE void P(t2adrlabel_addr_unk_Rd_1_t2ADR)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rd) {
-    return P(pcrel)(ctx, ((ctx->pc + 4) & ~2) + (bs_get(addr, ctx->op) & ((1 << 12) - 1)), bs_get(Rd, ctx->op), PLM_ADR);
+    return P(pcrel)(ctx, ((ctx->base.pc + 4) & ~2) +
+                         (bs_get(addr, ctx->base.op) & ((1 << 12) - 1)),
+                    (struct arch_pcrel_info) {bs_get(Rd, ctx->base.op), PLM_ADR});
 }
 static INLINE void P(t2ldrlabel_addr_unk_Rt_5_t2LDRBpci)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
-    return P(pcrel)(ctx, ((ctx->pc + 4) & ~2) + (bs_get(addr, ctx->op) & ((1 << 12) - 1)), bs_get(Rt, ctx->op), get_thumb2_load_mode(ctx->op));
+    return P(pcrel)(ctx, ((ctx->base.pc + 4) & ~2) +
+                         (bs_get(addr, ctx->base.op) & ((1 << 12) - 1)),
+                    (struct arch_pcrel_info) {bs_get(Rt, ctx->base.op),
+                                              get_thumb2_load_mode(ctx->base.op)});
 }
 static INLINE void P(uncondbrtarget_target_B_1_t2B)(tdis_ctx ctx, struct bitslice target) {
     int cc = ctx->arch.it_conds[0] != 0xe ? CC_ALREADY_IN_IT : 0;
-    return P(branch)(ctx, ctx->pc + 4 + 2 * sext(bs_get(target, ctx->op), 24), cc);
+    return P(branch)(ctx, ctx->base.pc + 4 + 2 * sext(bs_get(target, ctx->base.op), 24), cc);
 }
 static INLINE void P(unk_Rd_3_t2MOVTi16)(tdis_ctx ctx, struct bitslice Rd) {
     data(rout(Rd));
@@ -167,19 +172,20 @@ static INLINE void P(unk_Rt_13_VMOVRRD)(tdis_ctx ctx, UNUSED struct bitslice Rt)
 }
 
 static INLINE void P(thumb2_do_it)(tdis_ctx ctx) {
-    uint32_t op = ctx->op;
+    uint32_t op = ctx->base.op;
     #include "../generated/generic-dis-thumb2.inc.h"
     __builtin_abort();
 }
 
 static INLINE void P(dis_thumb2)(tdis_ctx ctx) {
-    ctx->op = *(uint32_t *) ctx->ptr;
-    ctx->op_size = 4;
+    ctx->base.op = *(uint32_t *) ctx->base.ptr;
+    ctx->base.op_size = ctx->base.newop_size = 2;
     /* LLVM likes to think about Thumb2 instructions the way the ARM manual
      * does - 15..0 15..0 rather than 31..0 as actually laid out in memory... */
-    ctx->op = flip16(ctx->op);
+    ctx->base.op = flip16(ctx->base.op);
     P(thumb2_do_it)(ctx);
     advance_it_cond(&ctx->arch);
-    TDIS_CTX_SET_NEWOP(ctx, flip16(TDIS_CTX_NEWOP(ctx)));
-    ctx->op = flip16(ctx->op);
+    uint32_t *newop_p = (uint32_t *) ctx->base.newop;
+    *newop_p = flip16(*newop_p);
+    ctx->base.op = flip16(ctx->base.op);
 }
diff --git a/lib/arm64/dis-main.inc.h b/lib/arm64/dis-main.inc.h
index 04349f2..06d391e 100644
--- a/lib/arm64/dis-main.inc.h
+++ b/lib/arm64/dis-main.inc.h
@@ -1,34 +1,34 @@
 static INLINE void P(adrlabel_label_unk_Xd_1_ADR)(tdis_ctx ctx, struct bitslice Xd, struct bitslice label) {
-    return P(pcrel)(ctx, ctx->pc + sext(bs_get(label, ctx->op), 22),
-                    bs_get(Xd, ctx->op), PLM_ADR);
+    return P(pcrel)(ctx, ctx->base.pc + sext(bs_get(label, ctx->base.op), 22),
+                    (struct arch_pcrel_info) {bs_get(Xd, ctx->base.op), PLM_ADR});
 }
 static INLINE void P(adrplabel_label_unk_Xd_1_ADRP)(tdis_ctx ctx, struct bitslice Xd, struct bitslice label) {
-    return P(pcrel)(ctx, ctx->pc + (sext(bs_get(label, ctx->op), 22) << 12),
-                    bs_get(Xd, ctx->op), PLM_ADR);
+    return P(pcrel)(ctx, ctx->base.pc + (sext(bs_get(label, ctx->base.op), 22) << 12),
+                    (struct arch_pcrel_info) {bs_get(Xd, ctx->base.op), PLM_ADR});
 }
 static INLINE void P(am_b_target_addr_B_1_B)(tdis_ctx ctx, struct bitslice addr) {
-    return P(branch)(ctx, ctx->pc + sext(bs_get(addr, ctx->op), 26) * 4,
+    return P(branch)(ctx, ctx->base.pc + sext(bs_get(addr, ctx->base.op), 26) * 4,
                      /*cc*/ 0);
 }
 static INLINE void P(am_bl_target_addr_1_BL)(tdis_ctx ctx, struct bitslice addr) {
-    return P(branch)(ctx, ctx->pc + sext(bs_get(addr, ctx->op), 26) * 4,
+    return P(branch)(ctx, ctx->base.pc + sext(bs_get(addr, ctx->base.op), 26) * 4,
                      /*cc*/ 0);
 }
 static INLINE void P(ccode_cond_am_brcond_target_B_1_Bcc)(tdis_ctx ctx, struct bitslice cond, struct bitslice target) {
-    int bits = bs_get(cond, ctx->op);
+    int bits = bs_get(cond, ctx->base.op);
     /* Bcc with AL/NV (which is actually just another AL) is useless but possible. */
     int cc = bits >= 0xe ? 0 : (CC_ARMCC | bits);
-    return P(branch)(ctx, ctx->pc + sext(bs_get(target, ctx->op), 19) * 4, cc);
+    return P(branch)(ctx, ctx->base.pc + sext(bs_get(target, ctx->base.op), 19) * 4, cc);
 }
 static INLINE void P(am_tbrcond_target_B_4_TBNZW)(tdis_ctx ctx, struct bitslice target) {
-    P(branch)(ctx, ctx->pc + sext(bs_get(target, ctx->op), 14) * 4, CC_XBXZ);
-    if (TDIS_CTX_MODIFY(ctx)) {
+    P(branch)(ctx, ctx->base.pc + sext(bs_get(target, ctx->base.op), 14) * 4, CC_XBXZ);
+    if (ctx->base.modify) {
         /* ditto CBNZ on ARM */
-        int new_target = (TDIS_CTX_NEWVAL(ctx, 0) - ctx->pc) / 4;
-        unsigned new = bs_set(target, new_target, ctx->op);
-        if (TDIS_CTX_NEWVAL(ctx, 1))
+        int new_target = (ctx->base.newval[0] - ctx->base.pc) / 4;
+        unsigned new = bs_set(target, new_target, ctx->base.op);
+        if (ctx->base.newval[1])
             new ^= 1 << 24;
-        TDIS_CTX_SET_NEWOP(ctx, new);
+        *(uint32_t *) ctx->base.newop = new;
     }
 }
 static INLINE void P(am_brcond_target_B_4_CBNZW)(tdis_ctx ctx, struct bitslice target) {
@@ -37,31 +37,31 @@ static INLINE void P(am_brcond_target_B_4_CBNZW)(tdis_ctx ctx, struct bitslice t
 }
 static INLINE void P(am_ldrlit_label_unk_Rt_6_LDRDl)(tdis_ctx ctx, struct bitslice Rt, struct bitslice label) {
     enum pcrel_load_mode mode;
-    if ((ctx->op >> 26) & 1) {
-        switch (ctx->op >> 30) {
+    if ((ctx->base.op >> 26) & 1) {
+        switch (ctx->base.op >> 30) {
             case 0: mode = PLM_U32_SIMD; break;
             case 1: mode = PLM_U64_SIMD; break;
             case 2: mode = PLM_U128_SIMD; break;
             default: __builtin_abort();
         }
     } else {
-        switch (ctx->op >> 30) {
+        switch (ctx->base.op >> 30) {
             case 0: mode = PLM_U32; break;
             case 1: mode = PLM_U64; break;
             case 2: mode = PLM_S32; break;
             default: __builtin_abort();
         }
     }
-    return P(pcrel)(ctx, ctx->pc + sext(bs_get(label, ctx->op), 19) * 4,
-                    bs_get(Rt, ctx->op), mode);
+    return P(pcrel)(ctx, ctx->base.pc + sext(bs_get(label, ctx->base.op), 19) * 4,
+                    (struct arch_pcrel_info) {bs_get(Rt, ctx->base.op), mode});
 }
 static INLINE void P(GPR64_Rn_1_RET)(tdis_ctx ctx, UNUSED struct bitslice Rn) {
     return P(ret)(ctx);
 }
 
 static INLINE void P(dis)(tdis_ctx ctx) {
-    uint32_t op = ctx->op = *(uint32_t *) ctx->ptr;
-    ctx->op_size = 4;
+    uint32_t op = ctx->base.op = *(uint32_t *) ctx->base.ptr;
+    ctx->base.op_size = ctx->base.newop_size = 4;
     /* clang doesn't realize that this is unreachable and generates code like
      * "and ecx, 0x1f; cmp ecx, 0x1f; ja abort".  Yeah, nice job there. */
     #include "../generated/generic-dis-arm64.inc.h"
diff --git a/lib/dis.h b/lib/dis.h
index 7455749..ed3690f 100644
--- a/lib/dis.h
+++ b/lib/dis.h
@@ -86,23 +86,24 @@ static const unsigned null_op = -0x100;
 #define data_flags(...) data_(__VA_ARGS__, rnull, rnull, rnull, rnull)
 #define data_(...) data__(__VA_ARGS__)
 #define data__(fl, b1, o1, v1, b2, o2, v2, b3, o3, v3, b4, o4, v4, ...) do { \
+    unsigned op = ctx->base.op; \
     P(data)(ctx, \
-        v1 ? bs_get(b1, ctx->op) : null_op, \
-        v2 ? bs_get(b2, ctx->op) : null_op, \
-        v3 ? bs_get(b3, ctx->op) : null_op, \
-        v4 ? bs_get(b4, ctx->op) : null_op, \
+        v1 ? bs_get(b1, op) : null_op, \
+        v2 ? bs_get(b2, op) : null_op, \
+        v3 ? bs_get(b3, op) : null_op, \
+        v4 ? bs_get(b4, op) : null_op, \
         (o1 << 0) | \
         (o2 << 1) | \
         (o3 << 2) | \
         (o4 << 3) | \
         fl); \
-    if (TDIS_CTX_MODIFY(ctx)) { \
-        unsigned new = ctx->op; \
-        new = bs_set(b1, TDIS_CTX_NEWVAL(ctx, 0), new); \
-        new = bs_set(b2, TDIS_CTX_NEWVAL(ctx, 1), new); \
-        new = bs_set(b3, TDIS_CTX_NEWVAL(ctx, 2), new); \
-        new = bs_set(b4, TDIS_CTX_NEWVAL(ctx, 3), new); \
-        TDIS_CTX_SET_NEWOP(ctx, new); \
+    if (DIS_MAY_MODIFY && ctx->base.modify) { \
+        uint32_t new = ctx->base.op; \
+        new = bs_set(b1, ctx->base.newval[0], new); \
+        new = bs_set(b2, ctx->base.newval[1], new); \
+        new = bs_set(b3, ctx->base.newval[2], new); \
+        new = bs_set(b4, ctx->base.newval[3], new); \
+        *(uint32_t *) ctx->base.newop = new; \
     } \
     return; \
 } while (0)