Refactor disassembly so x86 works, and add x86 transform-dis.

This patch is a monolithic mess, because I was too lazy to do the
refactor first (that would require some stash fun, since I wasn't
actually sure before doing x86 transform-dis what would be needed).

Anyway, the resulting code should be cleaner - less duplication.

This breaks ARM/ARM64.

4 files changed, 40 insertions, 36 deletions

diff --git a/lib/arm64/arch-dis.h b/lib/arm64/arch-dis.h
new file mode 100644
index 0000000..f91328b
--- /dev/null
+++ b/lib/arm64/arch-dis.h
@@ -0,0 +1,37 @@
+#pragma once
+#define MIN_INSN_SIZE 4
+#define TD_MAX_REWRITTEN_SIZE (7 * 2 * 4) /* also conservative */
+
+struct arch_pcrel_info {
+    unsigned reg;
+    enum pcrel_load_mode lm;
+};
+
+struct arch_dis_ctx {
+    /* For transform_dis only - used to get temporary registers.  We assume
+     * that we can use any caller-saved or IP register which was not written,
+     * so r9-r18.
+     * This is a massive overestimate: we just OR in each instruction's bits
+     * 4:0 (Rd for data, Rt for loads, most common), 14:10 (Rt2 for load-pair
+     * instructions), and 20:16 (Rs for store-exclusive insturctions).  It
+     * would be easy to restrict the latter two to the few instructions that
+     * actually use them, but with 10 available registers, and a patch of at
+     * most 3 instructions (and none of the instructions that require a temp
+     * use Rt2/Rs or could read their Rd, so the third doesn't count), we won't
+     * run out even with the dumbest possible thing. */
+    uint32_t regs_possibly_written;
+};
+
+static inline void arch_dis_ctx_init(struct arch_dis_ctx *ctx) {
+    ctx->regs_possibly_written = 0;
+}
+
+static inline int arm64_get_unwritten_temp_reg(struct arch_dis_ctx *ctx) {
+    uint32_t avail = ~ctx->regs_possibly_written & ((1 << 19) - (1 << 9));
+    if (!avail)
+        __builtin_abort();
+    return 31 - __builtin_clz(avail);
+}
+
+#define CC_ARMCC         (CC_CONDITIONAL | 0x400)
+#define CC_XBXZ          (CC_CONDITIONAL | 0x800)
diff --git a/lib/arm64/transform-dis-arm64.inc.h b/lib/arm64/arch-transform-dis.inc.h
index 792b835..d8f831d 100644
--- a/lib/arm64/transform-dis-arm64.inc.h
+++ b/lib/arm64/arch-transform-dis.inc.h
@@ -1,7 +1,7 @@
 #include "arm64/assemble.h"
 
 static NOINLINE UNUSED
-void transform_dis_pcrel(struct transform_dis_ctx *ctx, uintptr_t dpc, unsigned reg,
+void transform_dis_pcrel(struct transform_dis_ctx *ctx, uint_tptr dpc, unsigned reg,
                          enum pcrel_load_mode load_mode) {
     ctx->write_newop_here = NULL;
     void **codep = ctx->rewritten_ptr_ptr;
@@ -16,7 +16,7 @@ void transform_dis_pcrel(struct transform_dis_ctx *ctx, uintptr_t dpc, unsigned
 }
 
 static NOINLINE UNUSED
-void transform_dis_branch(struct transform_dis_ctx *ctx, uintptr_t dpc, int cc) {
+void transform_dis_branch(struct transform_dis_ctx *ctx, uint_tptr dpc, int cc) {
     /* TODO fix BL */
 #ifdef TRANSFORM_DIS_VERBOSE
     printf("transform_dis (%p): branch => %p\n", (void *) ctx->pc, (void *) dpc);
diff --git a/lib/arm64/dis-arm64.inc.h b/lib/arm64/dis-main.inc.h
index 04349f2..04349f2 100644
--- a/lib/arm64/dis-arm64.inc.h
+++ b/lib/arm64/dis-main.inc.h
diff --git a/lib/arm64/misc.h b/lib/arm64/misc.h
index f5a6154..066e9d5 100644
--- a/lib/arm64/misc.h
+++ b/lib/arm64/misc.h
@@ -1,36 +1,3 @@
 #pragma once
+#define TARGET_POINTER_SIZE 8
 #define TARGET_DIS_SUPPORTED
-#define TARGET_DIS_HEADER "arm64/dis-arm64.inc.h"
-#define TARGET_JUMP_PATCH_HDR "arm64/jump-patch.h"
-#define TARGET_TRANSFORM_DIS_HEADER "arm64/transform-dis-arm64.inc.h"
-#define MIN_INSN_SIZE 4
-#define TD_MAX_REWRITTEN_SIZE (7 * 2 * 4) /* also conservative */
-
-struct arch_dis_ctx {
-    /* For transform_dis only - used to get temporary registers.  We assume
-     * that we can use any caller-saved or IP register which was not written,
-     * so r9-r18.
-     * This is a massive overestimate: we just OR in each instruction's bits
-     * 4:0 (Rd for data, Rt for loads, most common), 14:10 (Rt2 for load-pair
-     * instructions), and 20:16 (Rs for store-exclusive insturctions).  It
-     * would be easy to restrict the latter two to the few instructions that
-     * actually use them, but with 10 available registers, and a patch of at
-     * most 3 instructions (and none of the instructions that require a temp
-     * use Rt2/Rs or could read their Rd, so the third doesn't count), we won't
-     * run out even with the dumbest possible thing. */
-    uint32_t regs_possibly_written;
-};
-
-static inline void arch_dis_ctx_init(struct arch_dis_ctx *ctx) {
-    ctx->regs_possibly_written = 0;
-}
-
-static inline int arm64_get_unwritten_temp_reg(struct arch_dis_ctx *ctx) {
-    uint32_t avail = ~ctx->regs_possibly_written & ((1 << 19) - (1 << 9));
-    if (!avail)
-        __builtin_abort();
-    return 31 - __builtin_clz(avail);
-}
-
-#define CC_ARMCC         (CC_CONDITIONAL | 0x400)
-#define CC_XBXZ          (CC_CONDITIONAL | 0x800)