some reorganization

3 files changed, 107 insertions, 0 deletions

diff --git a/lib/arm64/dis-arm64.inc.h b/lib/arm64/dis-arm64.inc.h
new file mode 100644
index 0000000..5317b89
--- /dev/null
+++ b/lib/arm64/dis-arm64.inc.h
@@ -0,0 +1,49 @@
+static INLINE void P(adrlabel_label_unk_Xd_1_ADR)(tdis_ctx ctx, struct bitslice Xd, struct bitslice label) {
+    return P(pcrel)(ctx, ctx->pc + sext(bs_get(label, ctx->op), 22), bs_get(Xd, ctx->op), PLM_ADR);
+}
+static INLINE void P(adrplabel_label_unk_Xd_1_ADRP)(tdis_ctx ctx, struct bitslice Xd, struct bitslice label) {
+    return P(pcrel)(ctx, ctx->pc + (sext(bs_get(label, ctx->op), 22) << 12), bs_get(Xd, ctx->op), PLM_ADR);
+}
+static INLINE void P(am_b_target_addr_B_1_B)(tdis_ctx ctx, struct bitslice addr) {
+    return P(branch)(ctx, ctx->pc + sext(bs_get(addr, ctx->op), 26) * 4, /*cond*/ false);
+}
+static INLINE void P(am_bl_target_addr_1_BL)(tdis_ctx ctx, struct bitslice addr) {
+    return P(branch)(ctx, ctx->pc + sext(bs_get(addr, ctx->op), 26) * 4, /*cond*/ false);
+}
+static INLINE void P(am_brcond_target_B_5_Bcc)(tdis_ctx ctx, struct bitslice target) {
+    return P(branch)(ctx, ctx->pc + sext(bs_get(target, ctx->op), 19) * 4, /*cond*/ true);
+}
+static INLINE void P(am_ldrlit_label_unk_Rt_6_LDRDl)(tdis_ctx ctx, struct bitslice Rt, struct bitslice label) {
+    enum pcrel_load_mode mode;
+    if ((ctx->op >> 26) & 1) {
+        switch (ctx->op >> 30) {
+            case 0: mode = PLM_U32_SIMD; break;
+            case 1: mode = PLM_U64_SIMD; break;
+            case 2: mode = PLM_U128_SIMD; break;
+            default: __builtin_abort();
+        }
+    } else {
+        switch (ctx->op >> 30) {
+            case 0: mode = PLM_U32; break;
+            case 1: mode = PLM_U64; break;
+            case 2: mode = PLM_S32; break;
+            default: __builtin_abort();
+        }
+    }
+    return P(pcrel)(ctx, ctx->pc + sext(bs_get(label, ctx->op), 19) * 4, bs_get(Rt, ctx->op), mode);
+}
+static INLINE void P(am_tbrcond_target_B_4_TBNZW)(tdis_ctx ctx, struct bitslice target) {
+    return P(branch)(ctx, ctx->pc + sext(bs_get(target, ctx->op), 14) * 4, /*cond*/ true);
+}
+static INLINE void P(GPR64_Rn_1_RET)(tdis_ctx ctx, UNUSED struct bitslice Rn) {
+    return P(ret)(ctx);
+}
+
+static INLINE void P(dis)(tdis_ctx ctx) {
+    uint32_t op = ctx->op = *(uint32_t *) ctx->ptr;
+    ctx->op_size = 4;
+    /* clang doesn't realize that this is unreachable and generates code like
+     * "and ecx, 0x1f; cmp ecx, 0x1f; ja abort".  Yeah, nice job there. */
+    #include "../generated/generic-dis-arm64.inc.h"
+    __builtin_abort();
+}
diff --git a/lib/arm64/misc.h b/lib/arm64/misc.h
new file mode 100644
index 0000000..672e1bd
--- /dev/null
+++ b/lib/arm64/misc.h
@@ -0,0 +1,6 @@
+#pragma once
+#define TARGET_DIS_SUPPORTED
+#define TARGET_DIS_HEADER "arm64/dis-arm64.inc.h"
+#define TARGET_TRANSFORM_DIS_HEADER "arm64/transform-dis-arm64.inc.h"
+#define MIN_INSN_SIZE 4
+struct arch_dis_ctx {};
diff --git a/lib/arm64/transform-dis-arm64.inc.h b/lib/arm64/transform-dis-arm64.inc.h
new file mode 100644
index 0000000..c47971b
--- /dev/null
+++ b/lib/arm64/transform-dis-arm64.inc.h
@@ -0,0 +1,52 @@
+static inline void MOVi64(struct transform_dis_ctx *ctx, int Rd, uint64_t val) {
+    int shift_nybbles = 0;
+    do {
+        int k = shift_nybbles != 0 ? 1 : 0;
+        op32(ctx, 0x69400000 | k << 28 | Rd | (val & 0xffff) << 4 | shift_nybbles << 20);
+        shift_nybbles++;
+        val >>= 16;
+    } while(val);
+}
+
+static inline void LDRxi(struct transform_dis_ctx *ctx, int Rt, int Rn, uint32_t off,
+                         bool regsize_64, enum pcrel_load_mode load_mode) {
+    int size, opc;
+    bool sign, simd;
+    switch (load_mode) {
+        case PLM_U8:  size = 0; sign = false;  simd = false; break;
+        case PLM_S8:  size = 0; sign = true;   simd = false; break;
+        case PLM_U16: size = 1; sign = false;  simd = false; break;
+        case PLM_S16: size = 1; sign = true;   simd = false; break;
+        case PLM_U32: size = 2; sign = false;  simd = false; break;
+        case PLM_S32: size = 2; sign = true;   simd = false; break;
+        case PLM_U64: size = 3; sign = false;  simd = false; break;
+        case PLM_U32_SIMD:  size = 2; opc = 1; simd = true; break;
+        case PLM_U64_SIMD:  size = 3; opc = 1; simd = true; break;
+        case PLM_U128_SIMD: size = 0; opc = 3; simd = true; break;
+        default: __builtin_abort();
+    }
+    if (simd) {
+        off /= 1 << (size | (opc & 1) << 2);
+    } else {
+        off /= 1 << size;
+        opc = sign ? (regsize_64 ? 2 : 3) : 1;
+    }
+    op32(ctx, 0x39000000 | Rt | Rn << 5 | off << 10 | opc << 22 | simd << 26 | size << 30);
+}
+
+
+static NOINLINE UNUSED void transform_dis_pcrel(struct transform_dis_ctx *ctx,
+        uintptr_t dpc, unsigned reg, enum pcrel_load_mode load_mode) {
+    ctx->write_newop_here = NULL;
+    if (load_mode >= PLM_U32_SIMD) {
+        /* use x0 as scratch */
+        op32(ctx, 0xf81f0fe0); /* str x0, [sp, #-0x10]! */
+        MOVi64(ctx, 0, dpc);
+        LDRxi(ctx, reg, 0, 0, true, load_mode);
+        op32(ctx, 0xf84107e0); /* ldr x0, [sp], #0x10 */
+    } else {
+        MOVi64(ctx, reg, dpc);
+        LDRxi(ctx, reg, reg, 0, true, load_mode);
+    }
+}
+