Ban calls within transform regions in threadsafe mode.

1 files changed, 28 insertions, 6 deletions

diff --git a/generated/generic-dis-thumb.inc.h b/generated/generic-dis-thumb.inc.h
index 42c6c20..50d095f 100644
--- a/generated/generic-dis-thumb.inc.h
+++ b/generated/generic-dis-thumb.inc.h
@@ -1,5 +1,5 @@
 /* Generated code; do not edit!
-   generated by tables/gen.js from imaon2 '2b8112204067abe3d0643e23c2486656841ecafe-dirty'
+   generated by tables/gen.js from imaon2 'f0e220720bbfb8f8e00e76af56806a28fc8739a2'
    https://github.com/comex/imaon2
    arguments: '--gen-hook-disassembler -n _thumb --dis-pattern=P(XXX) out/out-ARM.json'
    (fair warning: at present the main (Rust) code in that repository is barely
@@ -14,6 +14,7 @@
 /* GPR_Rm_1_tADDspr: tADDspr */
 /* t_adrlabel_addr_unk_Rd_1_tADR: tADR */
 /* t_brtarget_target_B_1_tB: tB */
+/* GPR_func_1_tBLXr: tBLXr */
 /* GPR_Rm_B_1_tBX: tBX */
 /* t_bcctarget_target_pred_p_B_1_tBcc: tBcc */
 /* t_cbtarget_target_B_2_tCBNZ: tCBNZ, tCBZ */
@@ -87,8 +88,9 @@
         }
     }
     case 3: {
-        switch ((op >> 8) & 0x1) {
-        case 0: {
+        switch ((op >> 7) & 0x3) {
+        case 0:
+        case 1: {
             switch ((op >> 15) & 0x1) {
             case 0: {
                 if ((op & 0xffffff00) == 0x4600) {
@@ -108,7 +110,7 @@
             }
             }
         }
-        case 1: {
+        case 2: {
             switch ((op >> 15) & 0x1) {
             case 0: {
                 if ((op & 0xffffff87) == 0x4700) {
@@ -127,6 +129,25 @@
             }
             }
         }
+        case 3: {
+            switch ((op >> 15) & 0x1) {
+            case 0: {
+                if ((op & 0xffffff87) == 0x4780) {
+                    struct bitslice func = {.nruns = 1, .runs = (struct bitslice_run[]) {{3,0,4}}};
+                    return P(GPR_func_1_tBLXr)(ctx, func); /* 0x00004780 | 0x00000078 */
+                } else {
+                    return P(unidentified)(ctx);
+                }
+            }
+            case 1: {
+                if ((op & 0xfffff800) == 0xc000) {
+                    goto insn_tGPR_Rn_reglist_regs_S_1_tSTMIA_UPD; /* 0x0000c000 | 0x000007ff */
+                } else {
+                    return P(unidentified)(ctx);
+                }
+            }
+            }
+        }
         }
     }
     case 4:
@@ -228,10 +249,10 @@
         }
     }
     case 31: {
-        if ((op & 0xff00) == 0xbf00) {
+        if ((op & 0xffffff00) == 0xbf00) {
             struct bitslice mask = {.nruns = 1, .runs = (struct bitslice_run[]) {{0,0,4}}};
             struct bitslice cc = {.nruns = 1, .runs = (struct bitslice_run[]) {{4,0,4}}};
-            return P(it_pred_cc_it_mask_mask_1_t2IT)(ctx, mask, cc); /* 0xbf00 | 0x00ff */
+            return P(it_pred_cc_it_mask_mask_1_t2IT)(ctx, mask, cc); /* 0x0000bf00 | 0x000000ff */
         } else {
             return P(unidentified)(ctx);
         }
@@ -242,6 +263,7 @@ static INLINE tdis_ret P(GPR_Rm_1_tADDspr)(struct bitslice ctx, struct bitslice
 static INLINE tdis_ret P(GPR_Rm_B_1_tBX)(struct bitslice ctx, struct bitslice Rm) {}
 static INLINE tdis_ret P(GPR_Rm_unk_Rd_1_tMOVr)(struct bitslice ctx, struct bitslice Rd, struct bitslice Rm) {}
 static INLINE tdis_ret P(GPR_Rm_unk_Rdn_1_tADDhirr)(struct bitslice ctx, struct bitslice Rdn, struct bitslice Rm) {}
+static INLINE tdis_ret P(GPR_func_1_tBLXr)(struct bitslice ctx, struct bitslice func) {}
 static INLINE tdis_ret P(it_pred_cc_it_mask_mask_1_t2IT)(struct bitslice ctx, struct bitslice mask, struct bitslice cc) {}
 static INLINE tdis_ret P(reglist_regs_1_tPOP)(struct bitslice ctx, struct bitslice regs) {}
 static INLINE tdis_ret P(reglist_regs_S_1_tPUSH)(struct bitslice ctx, struct bitslice regs) {}