diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/insns-arm.S (renamed from test/arm-insns.S) | 0 | ||||
| -rw-r--r-- | test/insns-libz-arm.S | 444 | ||||
| -rw-r--r-- | test/test-jump-dis.c | 12 | ||||
| -rw-r--r-- | test/test-td-simple.c | 49 |
4 files changed, 480 insertions, 25 deletions
diff --git a/test/arm-insns.S b/test/insns-arm.S index 62b4b48..62b4b48 100644 --- a/test/arm-insns.S +++ b/test/insns-arm.S diff --git a/test/insns-libz-arm.S b/test/insns-libz-arm.S new file mode 100644 index 0000000..e288e79 --- /dev/null +++ b/test/insns-libz-arm.S @@ -0,0 +1,444 @@ +#ifdef THUMB2 +.thumb +.thumb_func +.syntax unified +#endif +_deflateInit2_: +@ BB#0: + push {r4, r5, r6, r7, lr} + add r7, sp, #12 + sub sp, #88 + ldr.w r9, [r7, #20] + ldr.w r12, [r7, #16] + ldr.w lr, [r7, #12] + ldr r4, [r7, #8] + movs r5, #0 + movt r5, #0 + movs r6, #1 + movt r6, #0 +#if 0 /* just cutting out some insns so it all fits */ + str r0, [sp, #80] + str r1, [sp, #76] + str r2, [sp, #72] + str r3, [sp, #68] + str r4, [sp, #64] + str.w lr, [sp, #60] + str.w r12, [sp, #56] + str.w r9, [sp, #52] + str r6, [sp, #44] + ldr r0, [sp, #56] +#endif + cmp r0, r5 + beq LBB1_3 +@ BB#1: + movw r0, #123 + movt r0, #456 +LPC1_0: + add r0, pc + ldr r1, [sp, #56] + ldrsb.w r1, [r1] + ldrsb.w r0, [r0] + cmp r1, r0 + bne LBB1_3 +@ BB#2: + ldr r0, [sp, #52] + cmp r0, #56 + beq LBB1_4 +LBB1_3: + movw r0, #65530 + movt r0, #65535 + str r0, [sp, #84] + b LBB1_37 +LBB1_4: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #80] + cmp r1, r0 + bne LBB1_6 +@ BB#5: + movw r0, #65534 + movt r0, #65535 + str r0, [sp, #84] + b LBB1_37 +LBB1_6: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #80] + str r0, [r1, #24] + ldr r1, [sp, #80] + ldr r1, [r1, #32] + cmp r1, r0 + bne LBB1_8 +@ BB#7: + movs r0, #0 + movt r0, #0 + movw r1, #123 + movt r1, #456 +LPC1_1: + add r1, pc + ldr r1, [r1] + ldr r2, [sp, #80] + str r1, [r2, #32] + ldr r1, [sp, #80] + str r0, [r1, #40] +LBB1_8: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #80] + ldr r1, [r1, #36] + cmp r1, r0 + bne LBB1_10 +@ BB#9: + movw r0, #123 + movt r0, #456 +LPC1_2: + add r0, pc + ldr r0, [r0] + ldr r1, [sp, #80] + str r0, [r1, #36] +LBB1_10: + ldr r0, [sp, #76] + cmn.w r0, #1 + bne LBB1_12 +@ BB#11: + movs r0, #6 + movt r0, #0 + str r0, [sp, #76] +LBB1_12: + ldr r0, [sp, #68] + cmp r0, #0 + bge LBB1_14 +@ BB#13: + movs r0, #0 + movt r0, #0 + str r0, [sp, #44] + ldr r1, [sp, #68] + subs r0, r0, r1 + str r0, [sp, #68] + b LBB1_17 +LBB1_14: + ldr r0, [sp, #68] + cmp r0, #15 + ble LBB1_16 +@ BB#15: + movs r0, #2 + movt r0, #0 + str r0, [sp, #44] + ldr r0, [sp, #68] + subs r0, #16 + str r0, [sp, #68] +LBB1_16: + b LBB1_17 +LBB1_17: + ldr r0, [sp, #64] + cmp r0, #1 + blt LBB1_26 +@ BB#18: + ldr r0, [sp, #64] + cmp r0, #9 + bgt LBB1_26 +@ BB#19: + ldr r0, [sp, #72] + cmp r0, #8 + bne LBB1_26 +@ BB#20: + ldr r0, [sp, #68] + cmp r0, #8 + blt LBB1_26 +@ BB#21: + ldr r0, [sp, #68] + cmp r0, #15 + bgt LBB1_26 +@ BB#22: + ldr r0, [sp, #76] + cmp r0, #0 + blt LBB1_26 +@ BB#23: + ldr r0, [sp, #76] + cmp r0, #9 + bgt LBB1_26 +@ BB#24: + ldr r0, [sp, #60] + cmp r0, #0 + blt LBB1_26 +@ BB#25: + ldr r0, [sp, #60] + cmp r0, #4 + ble LBB1_27 +LBB1_26: + movw r0, #65534 + movt r0, #65535 + str r0, [sp, #84] + b LBB1_37 +LBB1_27: + ldr r0, [sp, #68] + cmp r0, #8 + bne LBB1_29 +@ BB#28: + movs r0, #9 + movt r0, #0 + str r0, [sp, #68] +LBB1_29: + movs r0, #0 + movt r0, #0 + movs r1, #1 + movt r1, #0 + movw r2, #5828 + movt r2, #0 + ldr r3, [sp, #80] + ldr r3, [r3, #32] + ldr.w r9, [sp, #80] + ldr.w r9, [r9, #40] + str r0, [sp, #36] @ 4-byte Spill + mov r0, r9 + blx r3 + str r0, [sp, #48] + ldr r0, [sp, #48] + ldr r1, [sp, #36] @ 4-byte Reload + cmp r0, r1 + bne LBB1_31 +@ BB#30: + movw r0, #65532 + movt r0, #65535 + str r0, [sp, #84] + b LBB1_37 +LBB1_31: + movs r0, #0 + movt r0, #0 + movs r2, #4 + movt r2, #0 + movs r1, #1 + movt r1, #0 + movs r3, #2 + movt r3, #0 + movw r9, #3 + movt r9, #0 + ldr.w r12, [sp, #48] + ldr.w lr, [sp, #80] + str.w r12, [lr, #28] + ldr.w r12, [sp, #80] + ldr.w lr, [sp, #48] + str.w r12, [lr] + ldr.w r12, [sp, #44] + ldr.w lr, [sp, #48] + str.w r12, [lr, #24] + ldr.w r12, [sp, #48] + str.w r0, [r12, #28] + ldr.w r12, [sp, #68] + ldr.w lr, [sp, #48] + str.w r12, [lr, #48] + ldr.w r12, [sp, #48] + ldr.w r12, [r12, #48] + lsl.w r12, r1, r12 + ldr.w lr, [sp, #48] + str.w r12, [lr, #44] + ldr.w r12, [sp, #48] + ldr.w r12, [r12, #44] + sub.w r12, r12, #1 + ldr.w lr, [sp, #48] + str.w r12, [lr, #52] + ldr.w r12, [sp, #64] + add.w r12, r12, #7 + ldr.w lr, [sp, #48] + str.w r12, [lr, #80] + ldr.w r12, [sp, #48] + ldr.w r12, [r12, #80] + lsl.w r12, r1, r12 + ldr.w lr, [sp, #48] + str.w r12, [lr, #76] + ldr.w r12, [sp, #48] + ldr.w r12, [r12, #76] + sub.w r12, r12, #1 + ldr.w lr, [sp, #48] + str.w r12, [lr, #84] + ldr.w r12, [sp, #48] + ldr.w r12, [r12, #80] + add.w r12, r12, #3 + sub.w r12, r12, #1 + str r0, [sp, #32] @ 4-byte Spill + mov r0, r12 + str r1, [sp, #28] @ 4-byte Spill + mov r1, r9 + str r3, [sp, #24] @ 4-byte Spill + str r2, [sp, #20] @ 4-byte Spill + bl ___udivsi3 + ldr r1, [sp, #48] + str r0, [r1, #88] + ldr r0, [sp, #80] + ldr r0, [r0, #32] + ldr r1, [sp, #80] + ldr r1, [r1, #40] + ldr r2, [sp, #48] + ldr r2, [r2, #44] + str r0, [sp, #16] @ 4-byte Spill + mov r0, r1 + mov r1, r2 + ldr r2, [sp, #24] @ 4-byte Reload + ldr r3, [sp, #16] @ 4-byte Reload + blx r3 + ldr r1, [sp, #48] + str r0, [r1, #56] + ldr r0, [sp, #80] + ldr r0, [r0, #32] + ldr r1, [sp, #80] + ldr r1, [r1, #40] + ldr r2, [sp, #48] + ldr r2, [r2, #44] + str r0, [sp, #12] @ 4-byte Spill + mov r0, r1 + mov r1, r2 + ldr r2, [sp, #24] @ 4-byte Reload + ldr r3, [sp, #12] @ 4-byte Reload + blx r3 + ldr r1, [sp, #48] + str r0, [r1, #64] + ldr r0, [sp, #80] + ldr r0, [r0, #32] + ldr r1, [sp, #80] + ldr r1, [r1, #40] + ldr r2, [sp, #48] + ldr r2, [r2, #76] + str r0, [sp, #8] @ 4-byte Spill + mov r0, r1 + mov r1, r2 + ldr r2, [sp, #24] @ 4-byte Reload + ldr r3, [sp, #8] @ 4-byte Reload + blx r3 + ldr r1, [sp, #48] + str r0, [r1, #68] + ldr r0, [sp, #48] + add.w r0, r0, #5824 + ldr r1, [sp, #32] @ 4-byte Reload + str r1, [r0] + ldr r0, [sp, #64] + adds r0, #6 + ldr r2, [sp, #28] @ 4-byte Reload + lsl.w r0, r2, r0 + ldr r3, [sp, #48] + movw r9, #5788 + movt r9, #0 + add r3, r9 + str r0, [r3] + ldr r0, [sp, #80] + ldr r0, [r0, #32] + ldr r3, [sp, #80] + ldr r3, [r3, #40] + ldr.w r9, [sp, #48] + movw r12, #5788 + movt r12, #0 + add r9, r12 + ldr.w r1, [r9] + str r0, [sp, #4] @ 4-byte Spill + mov r0, r3 + ldr r2, [sp, #20] @ 4-byte Reload + ldr r3, [sp, #4] @ 4-byte Reload + blx r3 + str r0, [sp, #40] + ldr r0, [sp, #40] + ldr r1, [sp, #48] + str r0, [r1, #8] + ldr r0, [sp, #48] + movw r1, #5788 + movt r1, #0 + add r0, r1 + ldr r0, [r0] + lsls r0, r0, #2 + ldr r1, [sp, #48] + str r0, [r1, #12] + ldr r0, [sp, #48] + ldr r0, [r0, #56] + ldr r1, [sp, #32] @ 4-byte Reload + cmp r0, r1 + beq LBB1_35 +@ BB#32: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #48] + ldr r1, [r1, #64] + cmp r1, r0 + beq LBB1_35 +@ BB#33: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #48] + ldr r1, [r1, #68] + cmp r1, r0 + beq LBB1_35 +@ BB#34: + movs r0, #0 + movt r0, #0 + ldr r1, [sp, #48] + ldr r1, [r1, #8] + cmp r1, r0 + bne LBB1_36 +LBB1_35: + movw r0, #123 + movt r0, #456 +LPC1_3: + add r0, pc + ldr r0, [r0] + movw r1, #666 + movt r1, #0 + ldr r2, [sp, #48] + str r1, [r2, #4] + ldr r0, [r0, #24] + ldr r1, [sp, #80] + str r0, [r1, #24] + ldr r0, [sp, #80] + bl _deflateEnd + movw r1, #65532 + movt r1, #65535 + str r1, [sp, #84] + str r0, [sp] @ 4-byte Spill + b LBB1_37 +LBB1_36: + ldr r0, [sp, #40] + ldr r1, [sp, #48] + movw r2, #5788 + movt r2, #0 + add r1, r2 + ldr r1, [r1] + movs r2, #1 + movt r2, #0 + lsrs r1, r2 + lsls r1, r1, #1 + add r0, r1 + ldr r1, [sp, #48] + movw r2, #5796 + movt r2, #0 + add r1, r2 + str r0, [r1] + ldr r0, [sp, #48] + ldr r0, [r0, #8] + ldr r1, [sp, #48] + movw r2, #5788 + movt r2, #0 + add r1, r2 + ldr r1, [r1] + movs r2, #3 + movt r2, #0 + muls r1, r2, r1 + add r0, r1 + ldr r1, [sp, #48] + movw r2, #5784 + movt r2, #0 + add r1, r2 + str r0, [r1] + ldr r0, [sp, #76] + ldr r1, [sp, #48] + str.w r0, [r1, #132] + ldr r0, [sp, #60] + ldr r1, [sp, #48] + str.w r0, [r1, #136] + ldr r0, [sp, #72] + ldr r1, [sp, #48] + strb.w r0, [r1, #36] + ldr r0, [sp, #80] + bl _deflateReset + str r0, [sp, #84] +LBB1_37: + ldr r0, [sp, #84] + add sp, #88 + pop {r4, r5, r6, r7, pc} + + diff --git a/test/test-jump-dis.c b/test/test-jump-dis.c new file mode 100644 index 0000000..161c80c --- /dev/null +++ b/test/test-jump-dis.c @@ -0,0 +1,12 @@ +#define JUMP_DIS_VERBOSE +#include <stdio.h> +#include "jump-dis-arm-multi.c" +#include <stdlib.h> +int main(UNUSED int argc, char **argv) { + static char buf[1048576]; + UNUSED size_t size = fread(buf, 1, sizeof(buf), stdin); + int patch_size = atoi(argv[1]); + int thumb = atoi(argv[2]); + bool bad = P(main)(buf, 0x10000, 0x10000 + patch_size, thumb); + printf("final: bad = %d\n", bad); +} diff --git a/test/test-td-simple.c b/test/test-td-simple.c index 7f11423..e1524f5 100644 --- a/test/test-td-simple.c +++ b/test/test-td-simple.c @@ -4,18 +4,22 @@ #define IF_BOTHER_WITH_MODIFY(...) __VA_ARGS__ #include "dis.h" -typedef struct { bool modify; } tdis_ret; typedef struct tc { uint32_t pc; + void *ptr; uint32_t op; uint32_t newop; uint32_t newval[4]; - + bool modify; + int op_size; } *tdis_ctx; #define P(x) P_##x +#define TDIS_CTX_MODIFY(ctx) ((ctx)->modify) +#define TDIS_CTX_NEWVAL(ctx, n) ((ctx)->newval[n]) +#define TDIS_CTX_SET_NEWOP(ctx, new) ((ctx)->newop = (new)) NOINLINE UNUSED -static tdis_ret P_data(struct tc *ctx, unsigned o0, unsigned o1, unsigned o2, unsigned o3, unsigned out_mask) { +static void P_data(struct tc *ctx, unsigned o0, unsigned o1, unsigned o2, unsigned o3, unsigned out_mask) { printf("data: %08x\n", ctx->op); unsigned os[] = {o0, o1, o2, o3}; for(size_t i = 0; i < 4; i++) { @@ -25,55 +29,50 @@ static tdis_ret P_data(struct tc *ctx, unsigned o0, unsigned o1, unsigned o2, un printf(" reg %x: %s\n", val, out_mask & (1 << i) ? "out" : "in"); ctx->newval[i] = i; } - return (tdis_ret) {true}; + ctx->modify = true; } NOINLINE UNUSED -static tdis_ret P_pcrel(struct tc *ctx, uint32_t dpc, unsigned reg, enum pcrel_load_mode lm) { +static void P_pcrel(struct tc *ctx, uint32_t dpc, unsigned reg, enum pcrel_load_mode lm) { printf("adr: %08x => %08x r%u lm:%d\n", ctx->op, dpc, reg, lm); - return (tdis_ret) {false}; + ctx->modify = false; } NOINLINE UNUSED -static tdis_ret P_ret(struct tc *ctx) { +static void P_ret(struct tc *ctx) { printf("ret: %08x\n", ctx->op); - return (tdis_ret) {false}; + ctx->modify = false; } NOINLINE UNUSED -static tdis_ret P_branch(struct tc *ctx, uint32_t dpc) { - printf("branch: %08x => %08x\n", ctx->op, dpc); - return (tdis_ret) {false}; +static void P_branch(struct tc *ctx, uint32_t dpc, bool cond) { + printf("branch(%s): %08x => %08x\n", cond ? "cond" : "uncond", ctx->op, dpc); + ctx->modify = false; } NOINLINE UNUSED -static tdis_ret P_unidentified(struct tc *ctx) { +static void P_unidentified(struct tc *ctx) { printf("unidentified: %08x\n", ctx->op); - return (tdis_ret) {false}; + ctx->modify = false; } NOINLINE UNUSED -static tdis_ret P_bad(struct tc *ctx) { +static void P_bad(struct tc *ctx) { printf("bad: %08x\n", ctx->op); - return (tdis_ret) {false}; + ctx->modify = false; } #include HDR -static tdis_ret P_dis(tdis_ctx ctx) { - unsigned op = ctx->op; - #include GENERATED_HEADER - /* clang doesn't realize that this is unreachable and generates code like - * "and ecx, 0x1f; cmp ecx, 0x1f; ja abort". Yeah, nice job there. */ - __builtin_abort(); -} +#define P_(x) P(x) int main(UNUSED int argc, char **argv) { struct tc ctx; ctx.pc = 0xdead0000; - ctx.op = (uint32_t) strtoll(argv[1] ? argv[1] : "deadbeef", NULL, 16); + uint32_t op = strtoll(argv[1] ? argv[1] : "deadbeef", NULL, 16); + ctx.ptr = &op; ctx.newop = 0; - P_dis(&ctx); - printf("==> %x\n", ctx.newop); + P_(xdis)(&ctx); + printf("==> %x (size=%d)\n", ctx.newop, ctx.op_size); } |