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-rw-r--r--lib/arm/arch-transform-dis.inc.h23
-rw-r--r--lib/arm/assemble.h20
-rw-r--r--lib/arm/dis-arm.inc.h7
-rw-r--r--lib/substitute-internal.h4
4 files changed, 39 insertions, 15 deletions
diff --git a/lib/arm/arch-transform-dis.inc.h b/lib/arm/arch-transform-dis.inc.h
index 4c44913..d74a06f 100644
--- a/lib/arm/arch-transform-dis.inc.h
+++ b/lib/arm/arch-transform-dis.inc.h
@@ -12,7 +12,8 @@ static struct assemble_ctx tdctx_to_actx(const struct transform_dis_ctx *ctx) {
}
return (struct assemble_ctx) {
ctx->rewritten_ptr_ptr,
- (uint_tptr) (uintptr_t) ctx->rewritten_ptr_ptr,
+ *ctx->rewritten_ptr_ptr,
+ (uint_tptr) (uintptr_t) *ctx->rewritten_ptr_ptr,
ctx->arch.pc_low_bit,
cond
};
@@ -20,8 +21,7 @@ static struct assemble_ctx tdctx_to_actx(const struct transform_dis_ctx *ctx) {
}
static int invert_arm_cond(int cc) {
- if (cc >= 0xe)
- __builtin_abort();
+ substitute_assert(cc < 0xe);
return cc ^ 1;
}
@@ -152,9 +152,10 @@ void transform_dis_pcrel(struct transform_dis_ctx *ctx, uint_tptr dpc,
static NOINLINE UNUSED
void transform_dis_branch(struct transform_dis_ctx *ctx, uint_tptr dpc, int cc) {
#ifdef TRANSFORM_DIS_VERBOSE
- printf("transform_dis (0x%llx): branch => 0x%llx\n",
+ printf("transform_dis (0x%llx): branch => 0x%llx cc=%x\n",
(unsigned long long) ctx->base.pc,
- (unsigned long long) dpc);
+ (unsigned long long) dpc,
+ cc);
#endif
/* The check in transform_dis_branch_top is correct under the simplifying
* assumption here that functions will not try to branch into the middle of
@@ -164,18 +165,23 @@ void transform_dis_branch(struct transform_dis_ctx *ctx, uint_tptr dpc, int cc)
transform_dis_branch_top(ctx, dpc, cc);
struct assemble_ctx actx = tdctx_to_actx(ctx);
ctx->write_newop_here = NULL;
+ int replacement_size = 8 + (actx.thumb ? 2 : 4);
if ((cc & CC_ARMCC) == CC_ARMCC) {
+ replacement_size += actx.thumb ? 2 : 4;
actx.cond = invert_arm_cond(cc & 0xf);
- Bccrel(actx, 2+8);
+ Bccrel(actx, replacement_size);
} else if ((cc & CC_CBXZ) == CC_CBXZ) {
+ replacement_size += 2;
ctx->base.modify = true;
- ctx->base.newval[0] = ctx->base.pc + 2+8;
+ ctx->base.newval[0] = actx.pc_of_code_base + replacement_size;
ctx->base.newval[1] = 1; /* do invert */
void **codep = ctx->rewritten_ptr_ptr;
ctx->write_newop_here = *codep; *codep += 2;
}
actx.cond = 0xe;
- LDR_PC(actx, dpc | ctx->arch.pc_low_bit);
+ MOVW_MOVT(actx, 14, dpc | ctx->arch.pc_low_bit);
+ BLXr(actx, 14);
+ substitute_assert(*actx.codep - actx.code_base == replacement_size);
}
static void transform_dis_pre_dis(struct transform_dis_ctx *ctx) {
@@ -193,6 +199,7 @@ static void transform_dis_pre_dis(struct transform_dis_ctx *ctx) {
static void transform_dis_post_dis(struct transform_dis_ctx *ctx) {
if (ctx->arch.bccrel_p) {
struct assemble_ctx actx = {&ctx->arch.bccrel_p,
+ ctx->arch.bccrel_p,
(uint_tptr) (uintptr_t) ctx->arch.bccrel_p,
/*thumb*/ true,
ctx->arch.bccrel_bits};
diff --git a/lib/arm/assemble.h b/lib/arm/assemble.h
index 2303a7a..1d4250b 100644
--- a/lib/arm/assemble.h
+++ b/lib/arm/assemble.h
@@ -3,11 +3,16 @@
struct assemble_ctx {
void **codep;
- uint_tptr pc;
+ void *code_base;
+ uint_tptr pc_of_code_base;
bool thumb;
int cond;
};
+static inline uint_tptr actx_pc(struct assemble_ctx ctx) {
+ return ctx.pc_of_code_base + (*ctx.codep - ctx.code_base);
+}
+
static inline void PUSHone(struct assemble_ctx ctx, int Rt) {
if (ctx.thumb)
op32(ctx.codep, 0x0d04f84d | Rt << 28);
@@ -63,7 +68,7 @@ static inline void LDRxi(struct assemble_ctx ctx, int Rt, int Rn, uint32_t off,
case PLM_U16: subop = 1; sign = 0; break;
case PLM_S16: subop = 1; sign = 1; break;
case PLM_U32: subop = 2; sign = 0; break;
- default: __builtin_abort();
+ default: substitute_assert(false);
}
op32(ctx.codep, 0x0000f890 | Rn | Rt << 28 | subop << 5 | sign << 8 |
off << 16);
@@ -85,11 +90,18 @@ static inline void LDRxi(struct assemble_ctx ctx, int Rt, int Rn, uint32_t off,
ctx.cond << 28);
break;
default:
- __builtin_abort();
+ substitute_assert(false);
}
}
}
+static inline void BLXr(struct assemble_ctx ctx, int Rm) {
+ if (ctx.thumb)
+ op16(ctx.codep, 0x4780 | Rm << 3);
+ else
+ op32(ctx.codep, 0xe12fff30 | Rm | ctx.cond << 28);
+}
+
static inline void Bccrel(struct assemble_ctx ctx, int offset) {
if (ctx.thumb) {
offset = (offset - 4) / 2;
@@ -101,7 +113,7 @@ static inline void Bccrel(struct assemble_ctx ctx, int offset) {
}
static inline void LDR_PC(struct assemble_ctx ctx, uint32_t dpc) {
- if (ctx.pc & 2)
+ if (actx_pc(ctx) & 2)
op16(ctx.codep, 0xbf00);
if (ctx.thumb)
op32(ctx.codep, 0xf000f8df);
diff --git a/lib/arm/dis-arm.inc.h b/lib/arm/dis-arm.inc.h
index 18285cd..021227c 100644
--- a/lib/arm/dis-arm.inc.h
+++ b/lib/arm/dis-arm.inc.h
@@ -164,7 +164,7 @@ static INLINE void P(adrlabel_label_unk_Rd_1_ADR)(tdis_ctx ctx, struct bitslice
}
static INLINE void P(br_target_target_pred_p_B_1_Bcc)(tdis_ctx ctx, struct bitslice target, struct bitslice p) {
unsigned p_val = bs_get(p, ctx->base.op);
- return P(branch)(ctx, ctx->base.pc + 8 + sext(bs_get(target, ctx->base.op), 24),
+ return P(branch)(ctx, ctx->base.pc + 8 + 4 * sext(bs_get(target, ctx->base.op), 24),
p_val == 0xe ? 0 : (CC_ARMCC | p_val));
}
static INLINE void P(ldst_so_reg_addr_unk_Rt_2_LDRB_PRE_REG)(tdis_ctx ctx, struct bitslice addr, struct bitslice Rt) {
@@ -210,8 +210,9 @@ static INLINE void P(GPR_func_3_BLX)(tdis_ctx ctx, UNUSED struct bitslice func)
return P(indirect_call)(ctx);
}
static INLINE void P(bl_target_func_2_BL)(tdis_ctx ctx, struct bitslice func) {
- return P(branch)(ctx, ctx->base.pc + 8 + sext(bs_get(func, ctx->base.op), 24),
- CC_CALL);
+ unsigned p_val = ctx->base.op >> 28; // XXX fix this to actually be an op
+ return P(branch)(ctx, ctx->base.pc + 8 + 4 * sext(bs_get(func, ctx->base.op), 24),
+ CC_CALL | (p_val == 0xe ? 0 : (CC_ARMCC | p_val)));
}
static INLINE void P(dis_arm)(tdis_ctx ctx) {
diff --git a/lib/substitute-internal.h b/lib/substitute-internal.h
index c9b78f0..2d26e66 100644
--- a/lib/substitute-internal.h
+++ b/lib/substitute-internal.h
@@ -109,3 +109,7 @@ static const char *xbasename(const char *path) {
return slash ? slash + 1 : path;
}
+#define substitute_assert(x) do { \
+ if (!(x)) { __builtin_abort(); } \
+} while(0)
+
Copyright (C) 2019-2021 Reiko Asakura. All Rights Reserved.