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-rw-r--r--generated/generic-dis-arm.inc.h33
1 files changed, 17 insertions, 16 deletions
diff --git a/generated/generic-dis-arm.inc.h b/generated/generic-dis-arm.inc.h
index e312884..88ce9ab 100644
--- a/generated/generic-dis-arm.inc.h
+++ b/generated/generic-dis-arm.inc.h
@@ -1,5 +1,5 @@
/* Generated code; do not edit!
- generated by tables/gen.js from imaon2 '2b8112204067abe3d0643e23c2486656841ecafe'
+ generated by tables/gen.js from imaon2 '2b8112204067abe3d0643e23c2486656841ecafe-dirty'
https://github.com/comex/imaon2
arguments: '--gen-hook-disassembler -n _arm --dis-pattern=P(XXX) out/out-ARM.json'
(fair warning: at present the main (Rust) code in that repository is barely
@@ -14,7 +14,7 @@
/* GPR_Rn_so_reg_reg_shift_unk_Rd_1_ADDrsr: ADDrsr */
/* adrlabel_label_unk_Rd_1_ADR: ADR */
/* GPR_dst_B_2_BX: BX, BX_pred */
-/* br_target_target_B_1_Bcc: Bcc */
+/* br_target_target_pred_p_B_1_Bcc: Bcc */
/* addr_offset_none_addr_unk_Rt_13_LDA: LDA, LDAB, LDAEX, LDAEXB, LDAEXD, LDAEXH, LDAH, LDREX, LDREXB, LDREXD, LDREXH, SWP, SWPB */
/* addrmode5_addr_8_LDC2L_OFFSET: LDC2L_OFFSET, LDC2_OFFSET, LDCL_OFFSET, LDC_OFFSET, VLDRD, VLDRS, VSTRD, VSTRS */
/* addr_offset_none_addr_4_LDC2L_OPTION: LDC2L_OPTION, LDC2_OPTION, LDCL_OPTION, LDC_OPTION */
@@ -123,9 +123,10 @@
return P(GPR_Rn_reglist_regs_S_16_STMDA)(ctx, regs, Rn); /* 0x08000000 | 0xf1efffff */
}
case 5: {
- insn_br_target_target_B_1_Bcc:;
+ insn_br_target_target_pred_p_B_1_Bcc:;
struct bitslice target = {.nruns = 1, .runs = (struct bitslice_run[]) {{0,0,24}}};
- return P(br_target_target_B_1_Bcc)(ctx, target); /* 0x0a000000 | 0xf0ffffff */
+ struct bitslice p = {.nruns = 1, .runs = (struct bitslice_run[]) {{28,0,4}}};
+ return P(br_target_target_pred_p_B_1_Bcc)(ctx, target, p); /* 0x0a000000 | 0xf0ffffff */
}
case 6:
return P(unidentified)(ctx);
@@ -191,7 +192,7 @@
return P(GPR_Rn_reglist_regs_16_LDMDA)(ctx, regs, Rn); /* 0x08100000 | 0xf1efffff */
}
case 1:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
}
}
case 3: {
@@ -232,7 +233,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_S_16_STMDA; /* 0x08000000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6: {
insn_addr_offset_none_addr_postidx_imm8s4_offset_S_4_STC2L_POST:;
struct bitslice offset = {.nruns = 2, .runs = (struct bitslice_run[]) {{0,0,8}, {23,8,1}}};
@@ -291,7 +292,7 @@
case 0:
goto insn_GPR_Rn_reglist_regs_16_LDMDA; /* 0x08100000 | 0xf1efffff */
case 1:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
}
}
case 3: {
@@ -352,7 +353,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_S_16_STMDA; /* 0x08000000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6: {
if ((op & 0xff00fd0) == 0xc400b10) {
goto insn_GPR_Rt_4_MCR; /* 0x0c400b10 | 0xf00ff02f */
@@ -405,7 +406,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_16_LDMDA; /* 0x08100000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6: {
if ((op & 0xff00ed0) == 0xc500a10) {
goto insn_unk_Rt_13_MRC; /* 0x0c500a10 | 0xf00ff12f */
@@ -449,7 +450,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_S_16_STMDA; /* 0x08000000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6:
goto insn_addr_offset_none_addr_postidx_imm8s4_offset_S_4_STC2L_POST; /* 0x0c200000 | 0xf0cfffff */
case 7: {
@@ -504,7 +505,7 @@
case 0:
goto insn_GPR_Rn_reglist_regs_16_LDMDA; /* 0x08100000 | 0xf1efffff */
case 1:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
}
}
case 3: {
@@ -609,7 +610,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_S_16_STMDA; /* 0x08000000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6: {
insn_addr_offset_none_addr_S_4_STC2L_OPTION:;
struct bitslice addr = {.nruns = 1, .runs = (struct bitslice_run[]) {{16,0,4}}};
@@ -674,7 +675,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_16_LDMDA; /* 0x08100000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6: {
insn_addr_offset_none_addr_4_LDC2L_OPTION:;
struct bitslice addr = {.nruns = 1, .runs = (struct bitslice_run[]) {{16,0,4}}};
@@ -728,7 +729,7 @@
case 4:
goto insn_GPR_Rn_reglist_regs_S_16_STMDA; /* 0x08000000 | 0xf1efffff */
case 5:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
case 6:
goto insn_addr_offset_none_addr_S_4_STC2L_OPTION; /* 0x0c800000 | 0xf04fffff */
case 7: {
@@ -778,7 +779,7 @@
case 0:
goto insn_GPR_Rn_reglist_regs_16_LDMDA; /* 0x08100000 | 0xf1efffff */
case 1:
- goto insn_br_target_target_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
+ goto insn_br_target_target_pred_p_B_1_Bcc; /* 0x0a000000 | 0xf0ffffff */
}
}
case 3: {
@@ -1936,7 +1937,7 @@ static INLINE tdis_ret P(addrmode5_pre_addr_S_4_STC2L_PRE)(struct bitslice ctx,
static INLINE tdis_ret P(addrmode_imm12_addr_unk_Rt_2_LDRBi12)(struct bitslice ctx, struct bitslice addr, struct bitslice Rt) {}
static INLINE tdis_ret P(addrmode_imm12_pre_addr_unk_Rt_2_LDRB_PRE_IMM)(struct bitslice ctx, struct bitslice addr, struct bitslice Rt) {}
static INLINE tdis_ret P(adrlabel_label_unk_Rd_1_ADR)(struct bitslice ctx, struct bitslice label, struct bitslice Rd) {}
-static INLINE tdis_ret P(br_target_target_B_1_Bcc)(struct bitslice ctx, struct bitslice target) {}
+static INLINE tdis_ret P(br_target_target_pred_p_B_1_Bcc)(struct bitslice ctx, struct bitslice target, struct bitslice p) {}
static INLINE tdis_ret P(ldst_so_reg_addr_unk_Rt_2_LDRB_PRE_REG)(struct bitslice ctx, struct bitslice addr, struct bitslice Rt) {}
static INLINE tdis_ret P(ldst_so_reg_shift_unk_Rt_2_LDRBrs)(struct bitslice ctx, struct bitslice shift, struct bitslice Rt) {}
static INLINE tdis_ret P(tcGPR_Rm_unk_Rd_1_MOVr_TC)(struct bitslice ctx, struct bitslice Rm, struct bitslice Rd) {}
Copyright (C) 2019-2021 Reiko Asakura. All Rights Reserved.